1. Field of the Invention
This invention relates to a reactive ion etching method applied in the process of manufacturing a semiconductor, and more particularly, to a method of etching an object mass containing an interposed thin insulation layer prepared from silicon dioxide, silicon nitride or the like.
2. Description of the Prior Art
As a semiconductor integrated circuit increases in density, the patterned size of its gate material and wiring material is reduced to less than 1 micron. For the formation of such an extremely fine pattern, reactive ion etching is now considered indispensable as an art of effectively etching exactly the true patterned size of, for example, a resist mask. This reactive ion etching allows for anisotropic etching. The fundamental principle of said reactive ion etching (illustrated in FIG. 1) is described below. High frequency power is impressed in a decompressed condition between a pair of flat parallel electrode plates which are set opposite each other (namely, the upper electrode plate 1, for example, is grounded, and high frequency power is impressed on the lower electrode plate 2, which is parallel to said upper electrode plate 2, from a high frequency power source 3 through an impedance matching device 4 and blocking capacitor 5). At this time, discharge takes place between both electrode plates 1, 2, giving rise to the distribution of D.C. potential between said electrode plates 1, 2. As a result, a noticeable D.C. potential difference (cathode drop voltage V.sub.dc) arises particularly in the vicinity of the lower electrode plate 2 which has been impressed with high frequency power. Referring to the above-mentioned D.C. potential distribution, V.sub.p denotes plasma potential. Positive voltage is impressed on the plasma side, while negative voltage is impressed on the lower electrode plate. The above-mentioned cathode drop voltage V.sub.dc arises from the fact that after the start of the discharge, a larger amount of electrons than positive ions is carried into the lower electrode plate 2, and consequently, the electrons are stored in said lower electrode plate 2. The magnitude of said cathode drop voltage V.sub.dc is determined by the difference between the mobilities of ions and electrons and the area ratio between cathode and anode. When, therefore discharge takes place in a reactive gas atmosphere mainly consisting of a halogen, the positive ions of the halogen are accelerated by the cathode drop voltage V.sub.dc in a D.C. field and are carried into the lower electrode plate 2 impressed with high frequency power or into an object to be etched placed on said lower electrode plate 2. Further description may now be made with reference to FIG. 2. Ions 8 of a reactive gas are not carried into that portion of the object of etching 6 in which the mask material 7 is mounted, namely, that portion thereof which is concealed by said mask material 7. Therefore, anisotropic etching true to the patterned size of a mask is effected.
In connection with the above-mentioned reactive ion etching process, reference is made to three conductive layers mounted on a semiconductor substrate with a thin insulation layer interposed therebetween. In this case, it sometimes happens that in the breakdown voltage test after etching, the damage to said insulation layer is detected.
Particularly in the case of, for example, an LSI element, high integration results in a decrease in the minimum width of said element, and further causes the thickness of an oxide gate membrane to be reduced to, for example, 400 .ANG. at 64 KDRAM, or 250 .ANG. at 256 KDRAM. When the aforementioned plasma etching was applied to a polycrystalline silicon layer, a refractory metal layer, or layer consisting of refractory metal silicide which was deposited on such an extremely thin oxide layer, then the underlying oxide layer was noticeably reduced in its breakdown voltage, thus failing to fully function as an insulation layer. In this connection, experimental data is set forth in FIG. 3A on the frequency of the damage to the oxide insulation layer. In comparison, FIG. 3B indicates experimental data on the frequency of the damage to the oxide insulation layer when the aforementioned polycrystalline silicon layer, the refractory metal layer, or the layer consisting of refractory metal silicide deposited on the extremely thin gate oxide layer was subjected to a chemical dry-etching process giving rise to no accumulation of electrical charge. Etching was applied to a phosphorus-doped polysilicon layer deposited on a silicon wafer with a gate oxide having a thickness of 400 .ANG.. FIGS. 3A and 3B indicate the relationship between the gate breakdown voltage (a breakdown electrical field as converted per 1 cm of thickness) and the number of damaged samples. The above-mentioned data clearly show that the reactive ion etching process damages the gate insulation layers on a larger number of samples in a region of lower voltage than the chemical dry etching process.